At the AI Infrastructure Summit in Santa Clara on September 16, an OpenAI researcher and an Intel architect pushed back on the idea that CXL memory can substitute for HBM in AI systems, SBS reported, citing Chosun Biz. Daniel Morris of OpenAI said he could not find a use case for CXL from the perspective of running AI models, and that its role might be limited to holding inactive data. Vidya Thiagarajan of Intel said CXL is not a replacement for HBM but a supplement to auxiliary storage, because data moving to and from GPUs over CXL is far slower than HBM. TrendForce carried the remarks on September 18.

The comments land as both Korean suppliers push CXL 3.2 products. Seoul Economic Daily reported in July that Samsung plans to mass-produce its CMM-D 3.0 module on CXL 3.2 within the year, and that SK hynix has shown a second-generation CMM-DDR5 sample on CXL 3.2 and begun customer sales talks, without a production schedule. SK hynix researchers also published ITME, an inference architecture that inserts CXL-hybrid memory between DDR and SSD to hold KV cache; the paper reports a 1.80× throughput gain over NVMe-oF disaggregated storage and up to 35.7% over a CPU-offload baseline.

Read carefully, the two sides are not in conflict. The suppliers position CXL as a tier below DRAM for cold KV cache and capacity expansion; the buyers say it is not HBM. The mechanism that matters for memory demand is whether CXL modules pull DRAM bits into a new socket, not whether they displace HBM. That question is settled by hyperscaler deployment volumes, which neither side disclosed.

The remarks do not change HBM demand or 2026–27 DRAM allocation. They do cap the near-term narrative for CXL as an "HBM alternative" and shift the burden to the suppliers to show paying customers.