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OpenAI and Anthropic are expected to begin purchasing memory directly from manufacturers in 2027, according to Aju Press, citing DIGITIMES. The report points to model developers taking a larger role in securing the components behind their computing infrastructure, although it does not disclose purchase volumes, pricing terms or delivery arrangements.

Direct relationships are already emerging. Micron announced an agreement with Anthropic in June, covering memory and storage supply, technical collaboration and a strategic investment. This broadens the story beyond Samsung and SK hynix and shows that the relationship is developing before the reported 2027 procurement shift.

For standard NVIDIA platforms, direct engagement with a memory supplier would still require coordination with the accelerator vendor. HBM must meet the platform’s design and qualification requirements. NVIDIA itself maintains a multi-year memory development and supply partnership with SK hynix.

The potential benefit for model developers is earlier control over supply allocation, delivery schedules and commercial terms. A reservation could, in principle, support systems built by an agreed manufacturing partner. Public disclosures do not establish that these arrangements provide transferable capacity rights or fixed memory prices. Custom ASIC programs offer greater scope for joint design, with the model developer, chip designer and memory supplier determining requirements together.

U.S. cloud service providers have raised their enterprise SSD demand forecasts over the past two weeks, TrendForce said on 21 September 2026. The research firm said recent procurement momentum suggests total enterprise SSD orders in 4Q26 could surpass the already elevated levels of 3Q26, and that this supports continued increases in enterprise SSD prices.

The evidence is an analyst reading of buyer behavior, not a disclosed contract. TrendForce did not name the CSPs, publish an order volume, or give a 4Q26 price range in its public release. It attributed the revision to major CSPs speeding up deployments and extending enterprise SSD use to more applications. It also said the increase is not confined to high-performance TLC. QLC has become a significant growth driver.

The base is already high. TrendForce estimated that combined revenue of the top five enterprise SSD brands reached US$37.59 billion in 2Q26, up 103.6% QoQ, driven by higher shipments and higher contract prices. Samsung ranked first at US$14.35 billion, followed by SK hynix at US$8.63 billion and Micron at US$6.98 billion. The new release extends that trajectory from 3Q26 into 4Q26. It does not introduce a new direction.

The mechanism runs through workloads beyond LLM training. TrendForce points to agentic AI systems that need large-scale real-time data retrieval and caching, and to vector databases, where QLC's capacity per dollar suits unstructured data. In China, it said DeepSeek-led architectures are pushing high-capacity QLC for KV cache offloading. If QLC takes a growing share of enterprise demand, suppliers can steer high-layer-count wafers toward enterprise products, where contract pricing is firmer, and away from client and mobile. TrendForce said the shift gives NAND suppliers greater control over capacity allocation and pricing in the enterprise segment.

The consumer side is moving differently. In its weekly spot update on 23 September, TrendForce reported 512Gb TLC wafer spot prices down 1.00% to US$19.883. It cited weak consumer demand and capacity releases from Chinese suppliers. Enterprise contract prices and wafer spot prices are separate markets, and this week they point in opposite directions. That split is the more useful reading: the enterprise segment is tightening through allocation, not through an industry-wide bit shortage.

The event has limits. A forecast upgrade is not a signed order, and an order is not revenue. The release says 4Q26 orders "could" exceed 3Q26 but does not say by how much. It adds no NAND wafer capacity, and it does not address server DRAM or HBM. It also does not show whether the revision reflects new demand or orders pulled forward from 1Q27 ahead of further price increases.

Three questions remain open. First, QLC mix growth could lift bits faster than average selling prices, since QLC is sold on cost per terabyte. Second, long-term agreements with price caps would limit how much of the gap between spot and contract prices suppliers can capture. Third, if Chinese capacity now feeding the spot market moves into qualified enterprise products, it would test supplier pricing power.

SK hynix's subsidiary Solidigm is considering building a NAND flash fab in the United States, with upstate New York the leading candidate site, Reuters reported on September 18, citing three people familiar with the matter. The sources said the project would be separate from SK hynix's discussions with Intel about making memory at Intel's Ohio site. One source cautioned that no agreement has been reached and key details remain under discussion.

The companies did not confirm a plan. SK hynix said Solidigm "is reviewing various options to strengthen its business competitiveness, but no specific plans have been confirmed." Solidigm said it does not comment on rumors and that no decision has been made. Reuters gave no figures for capacity, capital cost, node or timeline. This is an anonymous-source report of an evaluation, not an announcement.

The core issue is single-site exposure. Solidigm's only NAND fab is in Dalian, China, acquired from Intel in a $9 billion deal closed in 2020. That plant now runs on U.S. permission renewed yearly: the validated end-user status that let it receive chipmaking tools without shipment-by-shipment licenses expired at the end of 2025, and Tom's Hardware reported that the 2026 annual licenses for Dalian and Wuxi are designed to allow continued operation and maintenance rather than unrestricted expansion. In a 3D NAND business where cost per bit depends on migrating to higher layer counts, a fab that can be maintained but not freely upgraded is a slow structural disadvantage. A U.S. site would remove that ceiling and reduce exposure to potential U.S. tariffs.

The policy backdrop is two-sided. Reuters noted that the U.S. Commerce Secretary has threatened tariffs of up to 100% on Korean and Taiwanese firms that do not commit to U.S. production, while Seoul is pressing its chipmakers to invest in a domestic cluster and called the U.S. factory question "a matter of controversy." One source said NAND may draw less Korean resistance than HBM or DRAM because it is seen as less strategically sensitive.

The financial constraint is real. Reuters reported that Solidigm has posted years of losses since the acquisition, and that SK hynix said last month it was reviewing measures to strengthen the unit after reports of a pre-IPO fundraising of about 5 trillion won ($3.6 billion). U.S. production is more expensive than Korean production. Whether a U.S. fab would be funded by SK hynix, by outside capital through an IPO, or by public incentives is not disclosed, and Reuters does not link the two items.

For 2026–27 supply, this changes nothing. A greenfield NAND fab takes years from decision to wafer output, and no decision has been taken. Current NAND tightness driven by AI data-center demand is unaffected, and any output would arrive in a cycle whose demand Reuters itself described as uncertain. Competitive pressure is rising in parallel: CXMT plans a NAND R&D line in Beijing, and Chinese capacity continues to grow.

At the AI Infrastructure Summit in Santa Clara on September 16, an OpenAI researcher and an Intel architect pushed back on the idea that CXL memory can substitute for HBM in AI systems, SBS reported, citing Chosun Biz. Daniel Morris of OpenAI said he could not find a use case for CXL from the perspective of running AI models, and that its role might be limited to holding inactive data. Vidya Thiagarajan of Intel said CXL is not a replacement for HBM but a supplement to auxiliary storage, because data moving to and from GPUs over CXL is far slower than HBM. TrendForce carried the remarks on September 18.

The comments land as both Korean suppliers push CXL 3.2 products. Seoul Economic Daily reported in July that Samsung plans to mass-produce its CMM-D 3.0 module on CXL 3.2 within the year, and that SK hynix has shown a second-generation CMM-DDR5 sample on CXL 3.2 and begun customer sales talks, without a production schedule. SK hynix researchers also published ITME, an inference architecture that inserts CXL-hybrid memory between DDR and SSD to hold KV cache; the paper reports a 1.80× throughput gain over NVMe-oF disaggregated storage and up to 35.7% over a CPU-offload baseline.

Read carefully, the two sides are not in conflict. The suppliers position CXL as a tier below DRAM for cold KV cache and capacity expansion; the buyers say it is not HBM. The mechanism that matters for memory demand is whether CXL modules pull DRAM bits into a new socket, not whether they displace HBM. That question is settled by hyperscaler deployment volumes, which neither side disclosed.

The remarks do not change HBM demand or 2026–27 DRAM allocation. They do cap the near-term narrative for CXL as an "HBM alternative" and shift the burden to the suppliers to show paying customers.

On September 18, Reuters reported, citing three people with knowledge of the matter, that CXMT plans to set up a research-and-development production line for NAND flash at its new plant in Beijing, and has established a research institute there whose projects include NAND. One source said CXMT has discussed its plans with customers, including a newly established startup that wants NAND for AI and supercomputer storage. CXMT did not respond to Reuters. It was not clear when the line would start, or whether CXMT intends to go beyond trial production. No node, capacity or budget was disclosed.

CXMT is a DRAM company. TrendForce ranked it fourth in DRAM with a 9.5% share in 2Q26; in NAND, Samsung led with a 29.3% share. CXMT has capital to deploy after its 57.92 billion yuan ($8.6 billion) July IPO, and Reuters reported in August that it plans a second DRAM fab in Beijing.

The NAND market is short and expected to stay short: TrendForce estimates a 4–5% supply deficit in 2026, easing only in the second half of 2027, and expects Chinese suppliers to reach nearly 19% of global NAND bit output in 2027. A CXMT line that reached volume would add a second state-backed Chinese NAND supplier beside YMTC, which itself sent LPDDR samples to customers in April.

An R&D line is not capacity. It changes nothing in 2026–27 NAND supply or pricing. A new entrant must develop a 3D NAND process, reach yield and qualify with customers, each step measured in quarters and constrained by export controls on tools. The open questions are whether CXMT intends volume production at all, and how it splits capital between a second DRAM fab and NAND while DRAM and HBM carry the better returns.

Intel CEO Lip-Bu Tan said memory prices have risen five- to sevenfold and that conditions will get worse, in remarks reported on September 15 by Seoul Economic Daily. He called memory the main bottleneck in AI infrastructure and said projects are being delayed because companies cannot secure enough of it.

The figure is not usable as data. Intel published no transcript, the remarks reach us through secondary reporting, and the multiple carries no product, no base date and no price type. TrendForce places the comments at Splunk's .conf26 broadcast on September 16, a day later than the Korean account, so even the venue is unsettled.

Two other numbers from the same remarks are firmer and more useful. Tan said Intel can meet only about 50% of customer demand for processors, and that advanced packaging substrates come from four suppliers, two Japanese and two Taiwanese, whom Intel has to prepay to get attention. That is a large buyer treating prepayment as normal for a scarce input, the same behaviour now visible in memory long-term agreements.

What gives the remarks weight is the speaker's position. Suppliers describing shortage have an interest in the narrative; a buyer whose costs rise has the opposite one, and is describing delayed projects rather than disputed forecasts. None of it adds supply, and the squeeze he attributes to HBM reallocation is the same mechanism that leaves less capacity for general-purpose memory into 2027.

Samsung Electronics will add conventional DDR5 module output only through outside assembly partners, TheElec reported on September 16, citing industry sources. According to the report, Samsung lacks room to expand existing back-end lines at its Cheonan and Onyang campuses and is reallocating that space to advanced packaging, including HBM.

The report names the partners absorbing the work. Dreamtech is completing an expansion of its Noida plant in India this month, targeting annual capacity above 50 million units. Hanyang Digitech in Vietnam invested ₩31.5 billion in new machinery and automation in the first half of 2026. SFA Semicon in the Philippines is receiving DDR5 equipment transferred from Onyang, with first-phase operations scheduled for November. Samsung has not commented. These details come from industry sources and partner plans, not company disclosure.

The decision fits a pattern already visible in Samsung's capital plans. Korean media reported in August that Samsung would break ground this month on a ₩6 trillion HBM plant at Onyang. In May, Reuters reported that Samsung is building a roughly $1.5 billion test plant in Thai Nguyen, Vietnam, for legacy DRAM and NAND, with operations scheduled for November 2027. Leading-edge back-end capacity is being concentrated in Korea for HBM, while commodity assembly and test move to partners and lower-cost sites.

That split matters for how the constraint should be read. HBM is packaging-intensive: each stack requires thinned dies, through-silicon vias, stacking and extensive testing, which consume far more back-end tooling, floor space and engineering time than a standard module. A DDR5 module mounts finished packages on a circuit board. That is mature work that many firms can do. Moving it outside protects scarce Korean capacity for the step that is hardest to replicate.

The move also has clear limits. Outsourcing module assembly adds no DRAM wafer starts. It creates no HBM output until new packaging lines are built, tooled and qualified, and Samsung has not disclosed a completion date for the Onyang plant. In its second-quarter results, Samsung said that "despite efforts to increase production, supply constraints are expected to continue." Nothing in this report changes that assessment for 2026 or 2027.

Execution risk shifts as well. The report does not say whether outsourced volume includes server RDIMMs, which customers qualify closely, or only client modules. Partners introduce additional quality and scheduling variables, and some assembly margin moves outside Samsung, although that value is small relative to the DRAM inside each module. For DDR5 buyers, the practical question is whether partners scale quickly enough to keep assembly, rather than wafers, from becoming a local bottleneck.

Micron appointed Deirdre Hanford as president of Micron Research Labs on September 15, 2026, putting a semiconductor executive in charge of building its research infrastructure, operating model and external partnerships.

Announced in August, the Boise-based institution is backed by a planned $10 billion investment over the next decade. Construction is expected to begin in 2027. Its agenda spans memory process technologies, future memory and compute architectures, advanced packaging and next-generation manufacturing, with research extending beyond current product roadmaps.

Hanford brings decades of experience at Synopsys, including leadership of its Design Group and service as chief security officer. She was also the founding CEO of Natcast, the organization previously responsible for operating the National Semiconductor Technology Center. Her documented strengths lie in technology management, electronic design automation and coordinating industry, government and academia. Public biographies do not establish a comparable record of direct leadership in DRAM or NAND development.

That background could help Micron connect expertise across design, manufacturing and packaging, while strengthening recruitment and research partnerships. The appointment itself establishes no technical breakthrough. Its value will depend on the scientific team Hanford assembles and the lab’s ability to translate research into manufacturable technologies with measurable performance, energy-efficiency and cost advantages.

SanDisk's High Bandwidth Flash proposal addresses an expensive mismatch in AI infrastructure: systems may need additional accelerators partly to obtain more memory capacity, even when their compute requirements do not increase proportionately. By bringing dense NAND closer to compute, HBF could give system designers another way to accommodate large models.

SanDisk targets bandwidth comparable to HBM with eight to sixteen times the capacity at a similar cost. These are company claims, not established system-level economics. The comparison also requires a defined HBM generation, capacity and operating configuration. Greater capacity does not imply proportionately higher inference performance.

The engineering challenge is that bandwidth and access latency are different constraints. Many parallel NAND operations can deliver substantial aggregate throughput while individual reads remain slower than HBM accesses. Effective integration therefore depends on buffering, prefetching and workload scheduling. Recent FLINT research explicitly identifies NAND read latency and flash-management overhead as obstacles that an HBF architecture must address. FLINT research

This makes relatively stable model weights a compelling starting point. A system could retain frequently modified data in HBM while assigning larger, predominantly read-oriented datasets to HBF. The economic benefit would be strongest where memory capacity forces a model across more accelerators than its computational workload otherwise requires. In that situation, additional near-compute capacity could reduce hardware duplication and interconnect requirements. The benefit would be smaller where compute throughput or strict latency targets already determine accelerator count.

The evidence needs careful interpretation. SanDisk's published performance comparison uses internal simulation of pretrained-weight reads for Llama 3.1 405B, with hypothetical unlimited-capacity HBM as the reference. It does not establish equivalent performance across complete inference services, concurrent users or changing context lengths.

The more recent milestone is ecosystem development. SanDisk and SK Hynix announced an initial HBF specification through the Open Compute Project in August 2026, with Google and Tenstorrent participating in the consortium. Shared interfaces and implementation guidance can reduce adoption friction, although standardization remains distinct from commercial qualification and volume deployment.

For SanDisk, HBF creates a potential route into higher-value AI memory applications. However, attractive customer economics would not automatically guarantee attractive supplier margins. Specialized silicon, stacking, controllers, qualification and yield losses must be absorbed, while an open ecosystem may encourage competing implementations.

SK hynix’s exploratory talks with Intel could reshape its U.S. manufacturing footprint. According to Reuters, possible structures include leasing part of Intel’s Ohio site or forming a venture with Intel and major cloud customers. No agreement has been reached, and the memory technology, investment requirements and production schedule remain undisclosed. The significance lies in how such a partnership might redistribute manufacturing costs, supply commitments and investment risk. Reuters

Access to Ohio infrastructure could reduce some development work, but it would not provide immediately usable memory capacity. A memory fab requires a production flow configured for the selected technology, equipment installation, process qualification and a yield ramp. The talks do not establish that SK hynix would manufacture memory using Intel’s logic process nodes. Intel’s published schedule places initial operations at its first Ohio fab in 2030–2031; a partnership could change that schedule, but no revised timetable exists. Intel

The distinction between wafer fabrication and packaging is essential. SK hynix already has an advanced HBM packaging project in Indiana, targeting mass production in late 2029. If Ohio ultimately hosts memory wafer fabrication, it could complement that downstream investment. However, describing the proposed venture as an HBM factory would be premature: Reuters could not establish which chips it would produce. SK hynix

Potential cloud-customer participation is the most consequential economic feature. Equity contributions, prepayments or binding purchase commitments could lower SK hynix’s funding burden and reduce utilization risk. Customers, however, would likely seek compensation through pricing, priority allocation or investment returns. Better financing therefore would not automatically translate into higher margins. The relevant test is the project’s return on invested capital after construction costs, ramp losses and contractual concessions.

Political pressure could also influence the decision. Reuters reports pressure from Washington to localize production and potential Korean scrutiny of sensitive technology transfers. U.S. labor, construction and supply-chain costs could make the facility less competitive than an equivalent Korean investment. Subsidies, customer premiums or shared infrastructure might offset that disadvantage, but their value remains unknown. Strategic access to the U.S. market could justify some additional cost without making the project economically superior.

For Micron, a successful project could eventually challenge the differentiation associated with its expanding U.S. manufacturing base. Micron currently targets initial wafer output from its first new Idaho fab in mid-2027, although initial output is distinct from qualified volume shipments. SK hynix’s discussions do not yet establish a comparable production milestone. Micron

Micron’s demonstration of a 512GB DDR5 RDIMM advances server memory density, allowing larger datasets to remain in memory without adding DIMM slots. The module stacks DRAM dies using through-silicon vias (TSVs). AMD and Intel are validating the technology, with volume production targeted for the second half of 2027, aligned with customer needs.
The economic opportunity lies in supporting larger databases, greater virtualization density, and memory-intensive AI workloads within existing server footprints. However, higher capacity per DIMM does not automatically translate into greater aggregate DRAM demand: customers may consolidate modules rather than increase installed capacity.
The performance claims require context. Micron’s reported power reduction exceeding 60% compares one 512GB module with four 128GB modules, not total server power. System-level evaluation must account for bandwidth, channel utilization, and workload throughput alongside capacity. Likewise, the advertised 9,200 MT/s capability does not guarantee that operating speed across target platforms.