The HBM Enablers: What Marvell Reveals About the Next Layer of the Memory Cycle

Starting from Marvell’s latest earnings, this note examines how AI infrastructure enablers, including CXL, pooling, memory offload, and adjacent supply-chain technologies, are reshaping HBM economics and memory intensity.

SEPTEMBER 1, 2026·11 min read

The HBM Enablers: What Marvell Reveals About the Next Layer of the Memory Cycle

Marvell’s latest quarter should not be read as a simple bullish signal for memory. The more important message is that memory scarcity has moved from a pricing problem into a system-architecture problem.

That distinction matters because architecture is where a commodity cycle begins to defend itself. High prices are still evidence of real tightness. But those same prices are now forcing customers to recycle older DRAM, pool memory across servers, compress data, move warm data out of HBM, and reconsider memory content per system.

Read alongside Nvidia’s Q2 FY2027 filing, the picture is two-sided: the memory upcycle is still intact, but linear bit-per-system extrapolation does not.

For investors, the relevant identity is no longer “AI growth = memory growth.” HBM earnings power is a product of four moving variables:

AI accelerator / rack units × HBM GB per XPU × HBM ASP per GB × supplier margin.

Today, the first and third variables remain strongly supportive. The second is becoming more elastic. The fourth is increasingly company-specific.

1. Marvell: the news was the guidance delta

Marvell reported Q2 FY2027 revenue of $2.739 billion, up 37% year over year and 13% sequentially. Data Center revenue reached $2.172 billion, up 46% year over year and 18% sequentially, and represented 79% of total revenue. Non-GAAP gross margin was 58.9%, and non-GAAP diluted EPS was $0.94. The company guided Q3 revenue to $3.15 billion, ±5%.[1]

The quarter itself mattered less than the revision to the forward path. Marvell raised FY2027 revenue from roughly $11.5 billion to $12.0 billion, lifted FY2028 from $16.5 billion to $18.0 billion, and increased its FY2027 Data Center growth outlook from roughly 50% to 60%. It expects Data Center growth above 60% again in FY2028.[2]

That is important for memory because the architecture response is happening while AI infrastructure demand is still accelerating, not after demand has broken.

The most important memory-specific comment came in the CXL discussion. CEO Matt Murphy said CXL memory expansion is being deployed across multiple hyperscalers in very high volumes across multiple hyperscalers and explicitly linked that adoption to memory scarcity.[2]

The implication is straightforward: memory pricing is now changing customer architecture, not just customer budgets.

2. CXL is not a clean DRAM TAM extension

A bullish reading of CXL says it expands the amount of DRAM addressable by AI inference. That is true, but incomplete.

Marvell’s Structera S 30260 can connect 16 or 32 CPUs/GPUs to up to 48 TB of pooled memory, with up to 4 TB/s aggregate bandwidth and under 460 ns round-trip latency. That makes CXL useful as a warm capacity tier, not as a substitute for HBM or local DRAM on latency-critical hot paths.[3]

More important for the memory cycle is what happens underneath that pool. Marvell explicitly markets Structera X DDR4 support as enabling DIMM recycling. Its X 2404 controller can place retired DDR4 behind CXL in newer DDR5-only systems rather than scrapping still-functional memory.[4] Khurram Malik, Marvell’s memory and storage executive, described DDR4 recycling as the “first and foremost” CXL use case in an August interview.[5]

That is not a trivial detail. The first operational use case is not “buy more new bits.” It reuses old bits more efficiently.

Inline compression reinforces the same economics. Marvell says workload-dependent compression can materially raise effective capacity; those figures are vendor claims and should not be treated as independent production benchmarks.[4][5]

So CXL is best understood today as a cost-mitigation and utilization architecture rather than a clean DRAM TAM extension.

That does not make it automatically bearish. If recycling and pooling allow hyperscalers to ship more AI systems against a fixed bit pool, optimization can extend the upcycle. It becomes demand destruction only when memory intensity falls and compute/rack growth slows, and supply catches up.

3. Nvidia provides the hardest evidence that tightness is still real

If Marvell shows how customers are adapting, Nvidia shows the economic pain driving that adaptation.

Nvidia’s supply and capacity commitments jumped from $119 billion to $279 billion in one quarter. The company says those commitments are primarily related to memory procurement and manufacturing capacity. Of the $279 billion, $92 billion is scheduled for the remainder of FY2027, $87 billion for FY2028, $88 billion for FY2029, and $12 billion thereafter.[6][7]

Figure 3 — Nvidia supply and capacity commitments

For a cyclical component industry, that is extraordinary forward visibility. It is difficult to reconcile with a thesis that memory tightness has already peaked.

The same pressure is visible in Nvidia’s margin guidance. Non-GAAP gross margin was 75.0% in Q2 FY2027, is guided to roughly 74% in Q3, then 71–72% in Q4, before a partial recovery to 72–73% in FY2028 as Nvidia implements product price increases.[8]

Interpretation discipline matters here: memory is a major headwind, not the only driver of gross margin. Mix, packaging, and other component costs also move the line. But Nvidia’s own language — “extreme pricing conditions in memory” — makes the direction unambiguous.[8]

4. Elasticity has appeared; demand destruction has not been proven

The strongest bearish-looking evidence is also the easiest to misread.

TrendForce reports that Nvidia cut planned SOCAMM capacity per Vera CPU from 192 GB to 96 GB. On the same supply-chain reporting, LPDDR capacity per VR200 rack falls from roughly 55 TB to 28 TB. Yet the HBM4 content on the GPU side was reported to be unchanged at about 20.7 TB per rack.[9][10]

The key caveat is unusually important: TrendForce itself says the SOCAMM reduction does not represent lower aggregate memory demand. It is a response to insufficient LPDRAM allocation, with lower capacity per module intended to support higher module shipments.[9]

That is elasticity, but it is not yet demand destruction.

Rubin Ultra is even less settled. TrendForce’s latest rack-transition update says its HBM configuration and server architecture are still being finalized.[11] Lower-stack options are therefore a watch item, not a before/after production data point.

This distinction keeps the thesis falsifiable. A content reduction caused by scarcity can extend the cycle. The same content reduction becomes bearish when it persists in shipping SKUs while accelerator shipments slow and memory supply rises.

5. HBM is still the premium tier because the competition is now bandwidth per watt

Tiering does not eliminate HBM. It changes the question from “how much memory does the system need?” to “how much data must remain in the fastest, closest tier?”

That is why Nvidia’s new NVHBM architecture matters. Nvidia moves more of the memory-interface function into the HBM base die and claims three benefits versus standard HBM4E: up to 30% more memory bandwidth per stack, 15% lower HBM power, and up to 30% more usable main-die silicon.[12]

Those are Nvidia claims, not independent benchmarks, and should not be visualized as measured market data.

Figure 6 — NVHBM architecture and vendor claims

The investment implication does not require taking the percentages literally. The direction is enough: the next HBM competition is not only about GB per accelerator. It is increasingly about bandwidth density, power per bit, package area, thermal headroom, base-die integration, yield and qualification.

That creates an important asymmetry. HBM GB per XPU can flatten without collapsing HBM economics if bandwidth per stack and ASP per GB rise fast enough. Conversely, higher nominal HBM capacity does not guarantee superior supplier economics if yield, qualification, or pricing deteriorate.

6. Two memory-system optimization philosophies are forming

The useful split is not “open CXL versus closed NVLink.” Hyperscalers themselves operate proprietary systems. The better distinction is between two optimization philosophies.

Nvidia-integrated: HBM/NVHBM, CPU-attached memory and NVLink are co-designed to maximize bandwidth per watt and keep hot data close to the XPU.

Hyperscaler-disaggregated: HBM remains the hot tier, but CXL-pooled DRAM, near-memory compute, optical shared memory and SSD tiering are used to move warm data away from the most expensive layer.

Marvell’s expanded relationship with Google illustrates the second model. The disclosed program spans inference accelerators, storage controllers, NICs, memory-interface controllers, and near-memory compute. It is not a “memory-only” deal; it is evidence that memory placement and data movement have become part of custom AI-system design.[13]

Figure 7 — Two AI-memory optimization philosophies

Marvell’s Photonic Fabric and Bravera SC6 add further optionality. Photonic Fabric targets a shared warm-memory tier across racks, while Bravera SC6 aims to push colder KV-cache data toward NVMe SSDs. The SC6 is not yet an earnings driver: sampling is expected to begin in Q4 2026.[14]

For NAND suppliers, that is potentially positive for bit demand but less obviously positive for pricing power. Bravera is explicitly NAND-agnostic, and multi-vendor sourcing can shift economics toward the hyperscaler and controller provider.[14]

7. The investor framework: separate units, content, price, and margin

TrendForce now estimates that DRAM and NAND together will rise from 47% of major CSP capex in 2026 to 68% in 2027. Its August 25 note also says some LTAs signed from Q2 2026 onward include price ceilings, while customers may respond to elevated costs by reducing RDIMM or HBM content per system.[15]

TrendForce’s August 31 Server DIMM note adds a live behavioral signal: buyers are shifting toward mid- and lower-capacity modules to optimize TCO, while lower HBM stack specifications are flagged as a potential long-term lever on bit supply.[16]

That is why “bit demand” and “pricing power” cannot be treated as the same variable.

Figure 8 — HBM four-variable earnings identity

The four-variable HBM framework is:

Accelerator / rack units — Strong. AI infrastructure demand remains supported by Marvell’s guidance raises and Nvidia’s multi-year commitments.
HBM GB per XPU — Mixed. Current production HBM content remains high, but stack-height and system memory configurations are now active optimization variables.
HBM ASP per GB — Tight. Scarcity, wafer crowding, and long qualification cycles still support pricing, although contract structures matter.
Supplier margin — Company-specific. Yield, qualification mix, packaging, customer concentration, and LTA terms determine how much industry tightness becomes earnings.

This is also why we do not publish a single-point 2028 HBM deficit forecast from a reconstructed bit series in this note. Public data is sufficient to show direction, but not sufficient to turn a mixture of published ratios and analyst assumptions into an empirical-looking supply/demand chart without creating false precision.

What would falsify the current interpretation?

The thesis weakens materially if several of the following occur together:

HBM GB per XPU falls persistently in shipping production SKUs across multiple platforms.
Accelerator or rack shipment growth slows while memory-content optimization continues.
CXL recycling/pooling scales broadly while new server-DRAM bit demand stagnates.
HBM ASP falls faster than unit and bit growth can offset.
HBM yield and qualification improve faster than expected, removing the scarcity premium before demand compounds.
Major CSPs increasingly choose lower-memory configurations even after supply availability improves — evidence that optimization has moved from a scarcity workaround to a permanent TCO preference.

Conclusion: The cycle is intact, but the slope is no longer linear

Marvell and Nvidia now point to the same paradox from opposite sides.

Memory is scarce enough that Nvidia has committed hundreds of billions of dollars to future supply and is accepting a guided margin trough while it secures capacity. At the same time, those same prices are forcing hyperscalers to industrialize recycling, pooling, compression, tiering, and lower-content configurations.

That is not evidence that the memory upcycle has ended. It is evidence that the cycle has entered a more mature phase in which customers actively defend return on invested capital.

For HBM investors, compute growth alone is no longer sufficient. The critical question is whether accelerator-unit growth continues to outrun any decline in memory intensity while suppliers retain scarcity pricing and acceptable yields.

If it does, HBM earnings can continue to expand even as architectures become more efficient.

If it does not, the very tools built to survive the shortage will become the mechanism that cools it.

Sources

#Marvell #Dram #HBM #CXL #AIMemory #Memorycycle #MemoryHierarchy #EnterpriseSSD #NVIDIA